View ICS844001AGI_6665781.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

femtoclocks? crystal-to-lvds clock generator ics844001i idt ? / ics ? femtoclocks? clock generator 1 ics844001i rev a august 29, 2006 g eneral d escription the ics844001i is a fibre channel clock generator and a member of the hiperclocks tm family of high performance devices from idt. the ics844001i uses an 18pf parallel resonant crystal over the range of 20.4mhz - 28.3mhz. for fibre channel applications, a 26.5625mhz crystal is used. the frequency select pin allows the device to generate either 106.25mhz or 212.5mhz from a 26.5625mhz crystal. to generate 187.5mhz for 12gb ethernet, a 23.4375mhz crystal is used. the ics844001i uses idt?s 3 rd generation low phase noise vco technology and can achieve <1ps typical rms phase jitter, easily meeting fibre channel and ethernet jitter require- ments. the ics844001i is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? one differential lvds output ? crystal oscillator interface, 18pf parallel resonant crystal (20.4mhz - 28.3mhz) ? output frequency range: 81.66mhz - 226.66mhz ? vco range: 490mhz - 680mhz ? rms phase jitter @ 106.25mhz, using a 26.5625mhz crystal (637khz - 10mhz): 0.74ps (typical) ? 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s v dda gnd xtal_out xtal_in 1 2 3 4 v dd q nq freq_sel 8 7 6 5 b lock d iagram osc phase detector vco 490mhz - 680mhz m = 24 (fixed) 3 6 0 1 xtal_in xtal_out q nq c ommon c onfiguration t able - f ibre c hannel , 12gb e thernet p in a ssignment freq_sel pullup s t u p n i y c n e u q e r f t u p t u o ) z h m ( ) z h m ( y c n e u q e r f l a t s y r cl e s _ q e r fmn n o i t a c i l p i t l u m n / m e u l a v 5 2 6 5 . 6 214 26 4 5 2 . 6 0 1 5 2 6 5 . 6 204 23 8 5 . 2 1 2 5 7 3 4 . 3 204 23 8 5 . 7 8 1 ics844001i 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view
idt ? / ics ? femtoclocks? clock generator 2 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator t able 2. p in c haracteristics t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v a d d r e w o p. n i p y l p p u s g o l a n a 2d n gr e w o p. d n u o r g y l p p u s r e w o p 4 , 3 , t u o _ l a t x n i _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 5l e s _ q e r ft u p n ip u l l u p. n i p t c e l e s y c n e u q e r f 7 , 6q , q nt u p t u o. s l e v e l e c a f r e t n i s d v l . s t u p t u o k c o l c l a i t n e r e f f i d 8v d d r e w o p. n i p y l p p u s e r o c : e t o n p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ?
idt ? / ics ? femtoclocks? clock generator 3 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator t able 3a. p ower s upply dc c haracteristics , v dd = v dda = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 2 1 . 0 ?3 . 3v d d v i d d t n e r r u c y l p p u s r e w o p 5 1 1a m i a d d t n e r r u c y l p p u s g o l a n a 2 1a m a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, i o (lvds) contin uous current 10ma surge current 15ma package thermal impedance, ja 101.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 3c. lvcmos/lvttl dc c haracteristics , v dd = v dda = 3.3v5% or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i v d d v 3 . 3 =2v d d 3 . 0 +v v d d v 5 . 2 =7 . 1v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i v d d v 3 . 3 =3 . 0 -8 . 0v v d d v 5 . 2 =3 . 0 -7 . 0v i h i t n e r r u c h g i h t u p n il e s _ q e r fv d d v = n i v 5 2 6 . 2 r o v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n il e s _ q e r fv d d v , v 5 2 6 . 2 r o v 5 6 4 . 3 = n i v 0 =0 5 1 -a t able 3d. lvds dc c haracteristics , v dd = v dda = 3.3v5%, t a = -40c to 85c t able 3b. p ower s upply dc c haracteristics , v dd = v dda = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a d d e g a t l o v y l p p u s g o l a n av d d 2 1 . 0 ?5 . 2v d d v i d d t n e r r u c y l p p u s r e w o p 0 1 1a m i a d d t n e r r u c y l p p u s g o l a n a 2 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 5 35 1 40 8 4v m ? v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 5 2 2 . 15 2 3 . 15 2 4 . 1v ? v s o v s o e g n a h c e d u t i n g a m 0 5v m . n o i t a m r o f n i t u p t u o r o f n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r e s a e l p : e t o n
idt ? / ics ? femtoclocks? clock generator 4 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 4 . 0 23 . 8 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 ? e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m t able 5a. ac c haracteristics , v dd = v dda = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 6 6 . 1 86 6 . 6 2 2z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i @ z h m 5 2 . 6 0 1 z h m 0 1 - z h k 7 3 6 4 7 . 0s p : e g n a r n o i t a r g e t n i @ z h m 5 . 7 8 1 z h m 0 1 - z h k 7 3 6 8 4 . 0s p : e g n a r n o i t a r g e t n i @ z h m 5 . 2 1 2 z h m 0 1 - z h k 7 3 6 0 7 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 7 10 0 5s p c d oe l c y c y t u d t u p t u o 1 = l e s _ q e r f8 42 5% 0 = l e s _ q e r f5 45 5% . n o i t c e s s i h t g n i w o l l o f s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n t able 5b. ac c haracteristics , v dd = v dda = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 6 6 . 1 86 6 . 6 2 2z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n : e g n a r n o i t a r g e t n i @ z h m 5 2 . 6 0 1 z h m 0 1 - z h k 7 3 6 7 9 . 0s p : e g n a r n o i t a r g e t n i @ z h m 5 . 7 8 1 z h m 0 1 - z h k 7 3 6 8 5 . 0s p : e g n a r n o i t a r g e t n i @ z h m 5 . 2 1 2 z h m 0 1 - z h k 7 3 6 5 9 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 7 10 0 5s p c d oe l c y c y t u d t u p t u o 1 = l e s _ q e r f8 42 5% 0 = l e s _ q e r f5 45 5% . n o i t c e s s i h t g n i w o l l o f s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n t able 3e. lvds dc c haracteristics , v dd = v dda = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 0 30 9 30 8 4v m ? v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 0 . 12 . 15 2 3 . 1v ? v s o v s o e g n a h c e d u t i n g a m 0 5v m . n o i t a m r o f n i t u p t u o r o f n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r e s a e l p : e t o n
idt ? / ics ? femtoclocks? clock generator 5 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator t ypical p hase n oise at 106.25mh z @3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 o ffset f requency (h z ) n oise p ower dbc hz phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ? 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 212.5mh z @3.3v 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 212.5mhz rms phase jitter (random) 637khz to 10mhz = 0.70ps (typical) o ffset f requency (h z ) n oise p ower dbc hz phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ? 100 1k 10k 100k 1m 10m 100m 106.25mhz rms phase jitter (random) 637khz to 10mhz = 0.74ps (typical)
idt ? / ics ? femtoclocks? clock generator 6 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator p arameter m easurement i nformation o utput r ise /f all t ime o ffset v oltage s etup lvds 3.3v o utput l oad ac t est c ircuit lvds 2.5v o utput l oad ac t est c ircuit rms p hase j itter o utput d uty c ycle /p ulse w idth /p eriod scope qx nqx 3.3v5% power supply +? float gnd lvds q nq ? ? ? 100 out out lvds dc input v od / v od v dd out out lv d s dc input ? ? ? v os / v os v dd v dd v dd clock outputs 20% 80% 80% 20% t r t f v swing d ifferential o utput v oltage s etup scope qx nqx 2.5v5% power supply +? float gnd lvds phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power t pw t period t pw t period odc = x 100% v dd v dd v dda v dda
idt ? / ics ? femtoclocks? clock generator 7 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator a pplication i nformation figure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics844001i has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 26.5625mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics844001i provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v or 2.5v .01 f v dd
idt ? / ics ? femtoclocks? clock generator 8 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator 3.3v, 2.5v lvds d river t ermination a general lvds interface is shown in figure 4. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near f igure 4. t ypical lvds d river t ermination the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 2.5v or 3.3v + - vdd 100 ohm differential transmission line r1 100 lvds_driv er lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _ i n xta l _ o u t .1uf rs
idt ? / ics ? femtoclocks? clock generator 9 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics844001i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844001i is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (115ma + 12ma) = 440mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.440w *90.5c/w = 124.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 8-p in tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
idt ? / ics ? femtoclocks? clock generator 10 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator r eliability i nformation t ransistor c ount the transistor count for ics844001i is: 2533 t able 7. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w note: an airflow of 1 meter per second is strongly recommended.
idt ? / ics ? femtoclocks? clock generator 11 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator p ackage o utline - g s uffix for 8 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? femtoclocks? clock generator 12 ics844001i rev a august 29, 2006 ics844001i femtoclocks? crystal-to-lvds clock generator while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i g a 1 0 0 4 4 8 s c ii a 0 0 4p o s s t d a e l 8e b u tc 5 8 o t c 0 4 - t i g a 1 0 0 4 4 8 s c ii a 0 0 4p o s s t d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i g a 1 0 0 4 4 8 s c il i a 1 0p o s s t " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l i g a 1 0 0 4 4 8 s c il i a 1 0p o s s t " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics844001i femtoclocks? crystal-to-lvds clock generator

▲Up To Search▲

Price & Availability of ICS844001AGI

	To Download ICS844001AGI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .